As the market continuously drives price reduction of mobile phones and their components, it becomes increasingly important to reduce all costs associated with the fabrication of a system on chip (SoC) transceivers in cellular handsets. This includes the costs of final testing at production, which is required to constitute only a limited percentage of the total production cost. Additionally, high production yields are required, in order to maintain profitability, thus inhibiting the use of simplified overly-strict tests that would intolerably impact the yield.
Furthermore, customers are increasingly requiring smaller percentages of shipped defective devices, given in units of defective parts per million (DPPM), such that the test coverage and reliability expected from semiconductor manufacturers are demanding as well. Consequently, new testing environments and techniques are sought that would allow these conflicting goals to be met simultaneously.
In recent years, the semiconductor industry has been benefiting from automated means for inserting test circuitry into digital designs and calculating its coverage. The scan-chains used for this purpose provide structural testing, which typically targets the detection of silicon defects through symptoms such as “stuck at 0/1”, rather than functionally testing the circuitry. In contrast, in analog/RF designs, the structural approach is not as prevalent and is not built into the most commonly used analog computer aided design (CAD) tools. Radio transceivers have traditionally been designed in “analog friendly” fabrication processes, such as SiGe, with their production testing typically being based on high-cost testers having RF capabilities for both stimuli and measurements.
In addition, the recent trend toward SoC designs force transceiver implementations to adapt to digital design and fabrication environments. This has also created the need and the opportunity for lower cost testing techniques for the transceiver which approach those of the structural nature used for the greater digital portion of the SoC.
As an example, a diagram illustrating close-in spectral performance criteria for the transmitter, defined by the GSM wireless standard is shown in FIG. 1. The spectrum 4 of the output of the example transmitter is shown along with the spectral mask requirement 2. Additional performance criteria for the transmitter include the phase error during transmission, which indicates the modulation accuracy, and the far-out spectral mask. In a system that includes EDGE functionality, where non-constant envelope modulation is used, additional requirements are defined for the modulation accuracy, such as Error-Vector Magnitude (EVM).
Contrary to the GMSK constant envelope modulation of the original GSM system, the 8-PSK non-constant amplitude modulation for EDGE is extremely sensitive to the distortions that the power-amplification stages in the transmitter may introduce. These are known as AM-to-AM and AM-to-PM distortions. The former is a result of the gain curve not being perfectly linear, typically resulting in lower gain experienced for higher input signal levels, as saturation is approached, and the latter is typically caused by an amplitude-dependent phase-shift experienced in the non-linear stage. The transmitter chain elements, in which the modulated signal is created and amplified, must be tested at production and must also be characterized accurately enough for the predistortion mechanisms for them to be effective.
Other prior art techniques for a transceiver BIST involve testing the power amplifier using the receiver chain of the transceiver. This technique, however, is power inefficient as it requires both the transmit and receive chains for testing and calibration. Moreover, the environment of the system during actual application is not the same as during calibration. This is true for half-duplex systems in which the transmitter and receiver are not on at the same time.
These and other prior art measurement and characterization techniques are costly to implement, requiring additional circuitry and/or expensive external test equipment, and require impractically long test times to perform. For example, using conventional external RF test equipment would be cost prohibitive. On the other hand, a conventional very low cost tester (VLCT) is not capable of performing many of the required testing operations.
There is thus a need for a BIST mechanism that is capable of measuring and characterizing the power amplifier and other related internal components of the transmitter. The BIST mechanism should not require any external test equipment nor should it require any significant hardware overhead or operating conditions that depart from those of the normal operation, to the extent that the measurement/characterization may be impacted. Further, the BIST mechanism should reduce the required test time to a minimum and consume minimal power, such that it will not necessitate over-design of the internal power supply circuitry.